In semiconductor fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The formation of the various layers is achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, and epitaxial growth of silicon. Such techniques are described in S. M. Sze, VLSI Technology, 2nd ed., New York, McGraw-Hill, 1988, which is herein incorporated by reference for all purposes. Individual layers are patterned to create features and spaces, forming devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC). The patterning of the various device layers is achieved through lithography.
Lithography is the process for transferring images onto the substrate to define features. In general, a mask layer comprising, for example, photoresist is first formed on the surface of the substrate. The mask layer is then selectively exposed. Selective exposure of the mask layer is achieved using a mask and exposure source. Depending on whether a positive or negative resist is used, the exposed or unexposed regions are removed by etching to form the features.
A never ceasing demand for greater device integration has led to more densely packed ICs with smaller feature size. However, such advancements in technology have made it increasingly more difficult to form device structures consistently and reliably. For example, as dimensions decrease, alignment of structures in the various device layers requires greater precision. Additionally, proper exposure of the resist becomes problematic when imaging features of minimum dimensions, (i.e., the size of the feature is equal to about the wavelength of the exposure source). Underexposure and/or overexposure of the resist results in a defective or unreliable feature. Thus, a smaller process window exists for lithographic imaging of such structures. This causes process control problems, decreasing manufacturing reliability and yield.
To illustrate the difficulties resulting from a decrease in feature size, a discussion of interlevel connections is provided. Typically, interlevel connections are achieved using, for example, a dual-damascene process. In such a process, two sequential photoresist and etch steps are used to form the interlevel connections. For example, a first step is used to form a first contact opening or via to an underlying layer. A second in-line opening is then made to form a conductive line above the via. Both openings are then filled with aluminum.
The desire to form vias and trenches at about minimum dimensions causes problems that adversely affect the reliability of contacts formed. For example, light from the exposure source has a wavelength that is equal to about the mask openings or reticles that define the contact holes. Such a configuration makes it difficult for the lightwaves to pass through the reticles, resulting in an improper or underexposure of the photoresist. The underexposed photoresist prevents the contact holes from being completely opened by the etching process. As a result, the contact holes are not adequately filled with aluminum, degrading the reliability of the contacts formed.
The problem is aggravated by the difficulty in detecting such residual resist until after the contact fill has been added and the contact tested. The difficulty arises because the critical dimensions both at the top of the trench and at the top of the contact hole may be measured and found to be within the design specifications, even though there is a residue of photoresist in the contact hole of an amount sufficient to result eventually in a faulty contact.
One solution to the underexposure problem is to increase the intensity of the light used to expose the photoresist. This can overexpose the resist at some of the regions in which contact holes are to be formed. Overexposure enlarges the regions that is subsequently etched results in the formation of excessively large contact holes, which can result in shorts.
From the above discussion, it is desirable to form reliable structures, such as contacts, in the fabrication of ICs.